A feature-rich software toolkit that provides the building blocks to quickly and easily design high-performance video applications that use minimal CPU resources. This also includes a filter driver for GigE Vision 2 and RoCEv2 support for GigEVision 3 applications and an acquisition library for Windows or Linux along with sample applications, including a GigE Vision/ GenICam compliant viewer.

Allied Vision’s FPGA IP Cores are delivered as fully-working reference designs on an FPGA development kit. We support a wide range of off-the-shelf kits from AMD, Altera and Microchip.

Fully-functioning Reference Design: Allied Vision’s FPGA solutions are delivered as a self-contained, fully-functioning reference design that is running on an agreed common platform along with FPGA IP Cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Allied Vision cores are compact and leave enough space in the FPGA for your application.

Some parts of the design are delivered as binary files only (for example the GigE Vision control protocol library), while other parts are delivered as source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured as a GigE Vision camera system with a configurable test pattern generator. This system is delivered as a reference design for an off-the-shelf evaluation board. The reference design uses the AMD or Altera development tools (not in the scope of delivery).

Main new feature of GigE Vision 3 is the support of remote DMA/RoCEv2 for streaming. This offloads data reception fully to the RoCEv2 compatible network card, so that the CPU is not longer involved. This allows higher datarate above 10G.

To extend the functionality of the various reference boards, we provide FMC cards for 10G Ethernet with NBaseT support. 25G SFP28 interfaces are usually available on the eval boards.