- Compatible with AMD 7 Series (and newer)
- Compatible with Altera Cyclone 10 devices (and newer)
- Compatible with Microchip PolarFire
- Compact
- Customizable
- Speed support from 1 Gbps to 100 Gbps
- Delivered as working reference design
Architecture
CoaXPress (CXP) is a standard communication protocol for vision applications based on widely used coaxial cables. It allows easy interfacing between cameras and frame grabbers and supports the GenICam software standard. Sensor to Image offers a set of IP Cores and a development framework to build FPGA-based transmitters using the CoaXPress interface. Due to the speed of CXP, senders require a fast FPGA-based implementation of the CXP core, using embedded transceivers. CXP cores are compatible with AMD 7 series devices (and newer), Altera Cyclone 10 devices (and newer) and Microchip PolarFire Series.
Resource Usage
Download resource usageBenefits
MVDK Machine Vision Development Kit For CoaXPress
Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications. It supports CoaXPress host and device reference designs for various Enclustra FPGA modules with Altera and AMD FPGAs.
CoaXPress-Over-Fiber
A separate CoaXPress-over-Fiber Bridge IP Core is available to work with fiber cables, for longer distance, higher speed or in harsher environment.
Seamless Integration with Coaxlink Frame Grabbers
Excellent support by Coaxlink frame grabbers. The integrated Memento tool is a great help when debugging.
Supplied Reference Design
Fully-functioning Reference Design: S2I’s FPGA solutions are delivered as a self-contained, fully-functioning reference design that is running on an agreed common platform along with FPGA IP Cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.
Top Level Design
The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, CXP PHY) and FPGA internal data processing. We deliver this module as VHDL source code that can be adapted to custom hardware.
FPGA Integrated CPU
An FPGA integrated CPU (MicroBlaze, NIOS, ARM, Risc V) is used for several non-time-critical control and configuration tasks with the CXP-Device/Host core. This software is written in C and can be easily extended by the customer.
Video Acquisition Module
The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the final camera design.
Custom Configuration
Some parts of the design are delivered as binary files only (for example the CXP control protocol library), while other parts are delivered as source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured as a CXP camera system with a configurable test pattern generator. This system is delivered as a reference design for an off-the-shelf evaluation board. The reference design uses the AMD or Altera development tools (not in the scope of delivery).
FMC Interface Extensions
To extend the functionality of the various reference boards, we have designed FMC (FPGA Mezzanine Cards) that provide additional interfaces. We provide boards for CXP-6 and CXP-12 capable hardware with Microchip or Macom chipsets.
CXP Packet Composer
The CXP Streaming Interface receives all data from the video sensor output to the CXP PHY. It reaches the full speed on the streaming channel according to the CXP specification. The CXP Control Interface receives and sends all data from the CXP control channel, from and to the CXP PHY and implements the control channel according to the CXP specification. The CXP Packet Composer sends all data to the CXP transport layer controller, that implements the high speed interface to the FPGA transceivers. IP available with 32- or 64-bit wide data path for best resource – performance ratio.